Superconductor analog-to-digital converters are based on the ultra fast switching times of Josephson junction (JJ) comparators, of order a picosecond. This permits ultra fast sampling rates of tens of gigahertz, leading to some of the fastest circuits in any electronic technology for both Nyquist-rate ADCs and oversampling (sigma-delta and delta type) ADCs. See, for example, the review article on Superconducting ADCs by O. Mukhanov, et al., in Proc. IEEE, vol. 92, pp. 1564-1584 (2004), incorporated herein by reference. In order to further increase the dynamic range of superconductor ADCs, it is desirable to combine multiple JJ comparators together. One prior art approach was a flash ADC using a resistor network and multiple quantizers to generate an n-bit output, see for instance, U.S. Pat. No. 5,400,026 to Bradley. However, all designs based on resistor networks require precision matching of elements to achieve the best performance. Element mismatches will generate nonlinear artifacts, limiting the spur-free dynamic range (SFDR) that is essential for many ADC applications.
The problem of element mismatches is well known in the prior art of conventional semiconductor data converters. One general approach is known as “dynamic element matching” (DEM), in which various elements and comparators are permuted by physical switching in a way that randomizes the mismatches, sharply reducing the nonlinear peaks or “spurs”. See, for example, U.S. Pat. No. 6,816,103, to Jonsson, or U.S. Pat. No. 7,002,504 to McMahill.
The problem of using superconductor ADCs with multiple level sampling, or quantizing, while minimizing element mismatches is not solved.